1. Field of the Invention
The present invention relates generally to methods and systems for controlling a voltage at a node in a circuit such that the node is prevented from having an unknown floating voltage. More particularly, the invention relates to a method and a system for controlling nodes susceptible to floating voltages in a dynamic register included in a high speed communication integrated circuit while the integrated circuit is undergoing IDDQ testing for detection of circuit faults.
2. Background of Related Art
Local Area Networks (LAN) provides network connectivity for personal computers, workstations and servers. Ethernet, in its original 10BASE-T form, remains the dominant network technology for LANs. However, among the high speed LAN technologies available today, Fast Ethernet, or 100 BASE-T, has become the leading choice. Fast Ethernet technology provides a smooth, non-disruptive evolution from the 10 megabits per second (Mbps) performance of the 10BASE-T to the 100 Mbps performance of the 100BASE-T. The growing use of 100BASE-T connections to servers and desktops is creating a definite need for an even higher speed network technology at the backbone and server level.
The most appropriate solution to this need, now in development, is Gigabit Ethernet. Gigabit Ethernet will provide 1 gigabit per second (Gbps) bandwidth with the simplicity of Ethernet at lower cost than other technologies of comparable speed, and will offer a smooth upgrade path for current Ethernet installations.
In a Gigabit Ethernet communication system that conforms to the 1000 BASE-T standard, gigabit transceivers are connected via Category 5 twisted pairs of copper cables. Cable responses vary drastically among different cables. Thus, the computations, and hence power consumption, required to compensate for noise (such as echo, near-end crosstalk, far-end crosstalk) will vary widely depending on the particular cable that is used.
In integrated circuit technology, power consumption is generally recognized as being a function of the switching (clock) speed of transistor elements making up the circuitry, as well as the number of component elements operating within a given time period. The more transistor elements operating at one time, and the higher the operational speed of the component circuitry, the higher the relative degree of power consumption for that circuit. This is particularly relevant in the case of Gigabit Ethernet, since all computational circuits are clocked at 125 Mhz (corresponding to 250 Mbps per twisted pair of cable), and the processing requirements of such circuits require rather large blocks of computational circuitry, particularly in the filter elements. Power consumption figures in the range of from about 4.5 Watts to about 6.0 Watts are not unreasonable when the speed and complexity of modern gigabit communication circuitry is considered.
A Gigabit Ethernet transceiver includes a larger number of adaptive filters, which in turn require a large number of registers. Dynamic registers are preferred over static registers due to their low power consumption and faster operating speed. Thus, the requirements of small layout, low power consumption, and high operating speed of the Gigabit Ethernet transceiver necessitate the use of dynamic registers instead of static registers in most of the adaptive filters included in the Gigabit Ethernet transceiver. However, the use of dynamic registers poses a problem in IDDQ testing of the transceiver chip.
IDDQ testing, where IDDQ is the IEEE symbol for the quiescent current in CMOS integrated circuits, is a cost-effective test strategy for detecting faults in digital CMOS integrated circuits. IDDQ testing is ideal for static CMOS integrated circuits which draw extremely low leakage current IDD when no transistors are switching. This non-switching state is known as the quiescent state. Any defects in CMOS integrated circuits that cause a higher current than the assumed threshold value of IDD can be detected by this testing. When an integrated circuit includes a dynamic CMOS register, IDDQ testing becomes unreliable because floating nodes in the dynamic register may cause a substantial amount of power supply current to be dissipated in the dynamic register during the quiescent state. It is not possible to determine whether a large amount of power supply current drawn by the circuit was caused by a defect in the circuit or by floating nodes. Thus, floating nodes render the IDDQ test unreliable.
Thus, there is a need for a method and a system for controlling voltages at nodes that may become floating nodes in a dynamic register included in an integrated circuit while the integrated circuit is undergoing an IDDQ test.
The present invention is a method and a system for controlling a voltage at a node in a circuit such that the node is prevented from having an unknown floating voltage during a steady state of a clock signal. The circuit includes a transmission gate which has input and output terminals, and operates in response to a clock signal. The node is located proximal to the output terminal of the transmission gate. The method includes the operations of driving the node with an input signal when the transmission gate is open during a first steady state of the clock signal and pulling the node to a fixed voltage when the transmission gate is closed during a second steady state of the clock signal.